Abstract

The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will be based on four channels of 25 Gb/s. The corresponding transceivers in these optical links require a high-speed clock and data recovery circuit to extract a synchronous clock and recover the received data. To achieve a sufficiently fast settling time for 25 Gb/s burst mode upstream applications in passive optical networks (PONs), we introduce an architecture of the first 25 Gb/s all-digital clock and data recovery circuit (AD-CDR). Thanks to the implementation of a digital loop filter, our AD-CDR avoids the need of a system clock or a start-of-burst signal. This circuit is implemented in a 40-nm CMOS process and has a very compact active chip area of only 0.050 mm $^2$ . Furthermore, the performance of the burst-mode operation of our AD-CDR in an optical setup is measured and reported, resulting in a burst-mode lock time of 37.5 ns and consuming only 46 mW.

© 2017 IEEE

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