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Conferences > OFC > 2018 > Th4C > Th4C.2

FPGA Investigation on Error-Floor Performance of a Concatenated Staircase and Hamming Code for 400G-ZR Forward Error Correction

Yi Cai, Weiming Wang, Weifeng Qian, Jia Xing, Kai Tao, Junjie Yin, Shihua Zhang, Ming Lei, Erkun Sun, Ke Yang, Hungchang Chien, Qun Liao, and Huan Chen

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Abstract

With a record 200Gbps 50-piece-FPGA implementation, we investigate performance of a concatenated-staircase-Hamming code proposed for OIF-400GZR. FPGA emulations reveal an error flare at 10−10 BER lowering the predicted BER threshold from 1.25e−2 to 1.21e−2.

© 2018 The Author(s)

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