Abstract
Two attributes of fiber optics that have Impeded their utility in computer applications are that (1) they are inherently bit-serial while most computers are bit-parallel, and (2) few asynchronous clock recovery methods are available above 100 Mb/s where optical fibers are unmatched in speed. Traditional universal asynchronous receiver transmitter (UART) ICs are largely Inappropriate because edge timing is acquired by oversampling, which demands logic toggle rates 8-16 times higher than the data rate. This paper reports on a variation of the UART approach that trades slightly greater hardware complexity for a reduction in internal clock frequency thereby eliminating the need for extremely fast logic. Its simplicity makes It amenable to implementation with ECL gate arrays and semicustom GaAs logic. Potential applications include fiber-optic interfaces for computers, high-speed peripherals such as magnetic and optical disks, local area networks, and finally large parallel processing machines such as Hypercube.1
© 1987 Optical Society of America
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